p.9 Add_half

module Add-half (sum,c_out,a,b);

input a,b;
output sum,c_out;//declaration of port modes
wire c_out_bar;//內部接線 declaration of internal signal

//結構化模式 strutural module
xor(sum,a,b);
nand(c_out,bar,a,b);
not(c_out,c_out_bar);//instatiation of primitive gates


module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule



module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule