AOI_4_Unit

module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
reg y_out,y1,y2;//行為模式接線用reg
always
begin
#1 y1=x_in1 & x_in2;
#1 y2=x_in3 & x_in4;
#1 y_out=~(y1y2);
end
endmodule
/*
結構化模式：
module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1 (y1,x_in1,x_in2);
and #1 (y2,x_in3,x_in4);
nor #1 (y_out,y1,y2);
end
endmodule


系統時脈：
module top;
wire x_in1,x_in2,x_in3,x_in4;//input
wire y_out;//output
system_clock #200 clock1(x_in1);
system_clock #150 clock2(x_in2);
system_clock #100 clock1(x_in3);
system_clock #50 clock2(x_in4);
//-------------------------------------------
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule