延遲

module Compare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;

or(A_lt_B,w1,w2,w3);
nor(A_gt_B,A_lt_B,A_eq_B);
and(A_eq_B,w4,w5);
and(w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,A0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);

endmodule

AOI_4_Unit

module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
reg y_out,y1,y2;//行為模式接線用reg
always
begin
#1 y1=x_in1 & x_in2;
#1 y2=x_in3 & x_in4;
#1 y_out=~(y1y2);
end
endmodule
/*
結構化模式：
module AOI_4_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1 (y1,x_in1,x_in2);
and #1 (y2,x_in3,x_in4);
nor #1 (y_out,y1,y2);
end
endmodule


系統時脈：
module top;
wire x_in1,x_in2,x_in3,x_in4;//input
wire y_out;//output
system_clock #200 clock1(x_in1);
system_clock #150 clock2(x_in2);
system_clock #100 clock1(x_in3);
system_clock #50 clock2(x_in4);
//-------------------------------------------
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

p.9 Add_half

module Add-half (sum,c_out,a,b);

input a,b;
output sum,c_out;//declaration of port modes
wire c_out_bar;//內部接線 declaration of internal signal

//結構化模式 strutural module
xor(sum,a,b);
nand(c_out,bar,a,b);
not(c_out,c_out_bar);//instatiation of primitive gates


module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule



module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

Design a verilog textbench

題目：
Design a verilog model
of a half adder and
write a testbench to
verify the designed
verilog model.

CODE：

module Add_half (sum,c_out,a,b);

input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);

endmodule

verilog code1

2008/10/6

Verilog code1

//code
module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock#50 clock2(b);
always
#1 c=a&b;
endmodule

//text_bench
module system_clock(clk);

parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end

always @ (posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

code：

波形圖：